Minimal-Overlap Centrality for Multi-Gateway Designation in Real-Time TSCH Networks - INRIA Chile Access content directly
Journal Articles ACM Transactions on Embedded Computing Systems (TECS) Year : 2023

Minimal-Overlap Centrality for Multi-Gateway Designation in Real-Time TSCH Networks

Abstract

This article presents a novel centrality-driven gateway designation framework for the improved real-time performance of low-power wireless sensor networks (WSNs) at system design time. We target time-synchronized channel hopping (TSCH) WSNs with centralized network management and multiple gateways with the objective of enhancing traffic schedulability by design. To this aim, we propose a novel network centrality metric termed minimal-overlap centrality that characterizes the overall number of path overlaps between all the active flows in the network when a given node is selected as gateway. The metric is used as a gateway designation criterion to elect as a gateway the node leading to the minimal number of overlaps. The method is then extended to multiple gateways with the aid of the unsupervised learning method of spectral clustering. Concretely, after a given number of clusters are identified, we use the new metric at each cluster to designate as cluster gateway the node with the least overall number of overlaps. Extensive simulations with random topologies under centralized earliest-deadline-first (EDF) scheduling and shortest-path routing suggest our approach is dominant over traditional centrality metrics from social network analysis, namely, eigenvector, closeness, betweenness, and degree. Notably, our approach reduces by up to 40% the worst-case end-to-end deadline misses achieved by classical centrality-driven gateway designation methods.
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Dates and versions

hal-04170029 , version 1 (25-07-2023)

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  • HAL Id : hal-04170029 , version 1

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Gaitán Miguel Gutiérrez, Almeida Luís, D'Orey Pedro M., Santos Pedro M., Thomas Watteyne. Minimal-Overlap Centrality for Multi-Gateway Designation in Real-Time TSCH Networks. ACM Transactions on Embedded Computing Systems (TECS), 2023. ⟨hal-04170029⟩
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